Sr. Layout Designer

Job DescriptionJob Description

This senior role at a Series-D semiconductor startup involves owning physical layout design for high-performance ADC/DAC and SerDes circuits on advanced nodes (2nm–16nm). You will drive floorplanning and tape-out execution for AI data center infrastructure.

Mandatory Skills:

Technical: 10+ years in analog/mixed-signal layout with deep expertise in TSMC FinFET and Gate-All-Around (GAA).

Tools: Mastery of Cadence Virtuoso and Schematic-to-Layout (S2L) flows.

Fundamentals: Expert knowledge of matching, shielding, and electromigration for high-speed blocks.

Execution: Proven full tape-out experience, including LVS/DRC/ERC/PEX sign-off.

Candidates must possess a stable job history and mentor junior engineers. Scripting and SoC integration are .